The present invention relates generally to integrated circuit (IC) designs, and more particularly to a circuit for generating a pulse signal in response to an input clock signal.
A pulse generator is commonly used within an integrated circuit (IC) for providing a pulse signal with a constant pulse width. A conventional pulse generator is designed to generate the pulse signal in response to an input clock signal. The pulse generator typically includes an NAND gate device with one input terminal coupled to the input clock signal without delayed, and the other input terminal coupled to the input clock signal delayed in time. The NAND gate device generates an output that goes high when both the clock signal and the delayed clock signal are high. The output of the NAND gate device is inverted to generate the pulse signal.
Conventionally, the pulse width of the pulse signal is designed to be determined by the delay time of the clock signal passing through the delay module. However, this may not be true if the width of the clock signal is too short. As discussed above, the pulse signal is generated when both the clock signal and the delayed clock signal are at high states. If the high state of the clock is shorter than the high state of the delayed clock, it will cut short the pulse width of the pulse signal, and therefore increasing the risk of system error.
While some other pulse generators have been proposed to solve the problem caused by the insufficient clock width, they often have their own drawbacks and therefore present a separate set of challenges. Thus, it is desirable to design a new pulse generator that can generate the pulse signal, which is not cut short by the insufficient clock width.